All makers of dynamic random access memory (DRAM) strive to develop process technologies that allow them to build the smallest memory cells possible to make their chips cheaper. But this is not exactly the best strategy for China-based ChangXin Memory Technologies (CXMT), which has to comply with export restrictions of the U.S. government. Recently the company said that its 17nm production node is actually more like an 18.5nm technology, which allows it to get advanced wafer fab tools, reports DigiTimes.  

The U.S. sanctions against the Chinese semiconductor sector curbs Chinese DRAM makers from from procuring tools that can be used to build memory on a 18nm half-pitch node or more advanced. As a result, the company cannot get fab tools from American companies to build 18nm DRAMs. But CXMT has found a way. The company has allegedly notified U.S. authorities that its alleged 17nm process technology ‘falls short of the actual standard’ and is more like an 18.5nm-class node. Therefore, the new fabrication technology does not actually breach the regulations set by the sanctions, thus enabling CXMT to seemingly expand its 18.5nm-class capacity. 

The anticipated Phase 2 expansion is expected to add another 40,000 wafer starts per month capacity by the end of the year, positioning CXMT to capture around 10% of the global DRAM production capacity. But to build it, CXMT needs tools from companies like ASML, Applied Materials, and KLA, which is why it needs to persuade the U.S. government that its DRAMs do not violate the U.S. export rules. 

Like other Chinese chipmakers, CXMT is also leaning more on equipment made in China for the next phase of expansion at the Hefei plant. This move not only aligns with the company’s expansion plans but also demonstrates a commitment to reducing dependence on foreign technology and enhancing China’s self-sufficiency in the semiconductor sector.

With its ‘relaxed’ 18.5nm node, CXMT follows suit of Yangtze Memory Technologies Co. (YMTC), which last year introduced its 120-layer 3D NAND fabrication process to comply with the U.S. export rules which curb sales of wafer fab tools that enable Chinese entities to build 3D NAND with 128 layers or more.

Recently CXMT introduced a FinFET-based 18nm half-pitch process technology that violates all possible U.S. sanctions.